Assembly Language Operations
Conditional Branch Instructions
There are 16 possible conditional branches in the ARM assembly language, including "always" (which is effectively an unconditional branch) and "never" (which is never used but exists for future possible extensions to the architecture). The complete set of branch instructions is given in the table:
| Branch | Condition Test | Meaning | Uses |
| B | No test | Unconditional | Always take the branch |
| BAL | No test | Always | Always take the branch |
| BEQ | Z=1 | Equal | Comparison equal or zero result |
| BNE | Z=0 | Not equal | Comparison not equal or non-zero result |
| BCS | C=1 | Carry set | Arithmetic operation gave carry out |
| BCC | C=1 | Carry clear | Arithmetic operation did not produce a carry |
| BHS | C=1 | Higher or same | Unsigned comparison gave higher or same result |
| BLO | C=0 | Lower | Unsigned comparison gave lower result |
| BMI | N=1 | Minus | Result is minus or negative |
| BPL | N=0 | Plus | Result is positive (plus) or zero |
| BVS | V=1 | Overflow Set | Signed integer operation: overflow occurred |
| BVC | V=0 | Overflow Clear | Signed integer operation: no overflow occurred |
| BHI | ((NOT C) OR Z) =0 {C set and Z clear} |
Higher | Unsigned comparison gave higher |
| BLS | ((NOT C) OR Z) =1 {C set or Z clear} |
Lower or same | Unsigned comparison gave lower or same |
| BGE | (N EOR V) =0 {(N and V) set or (N and V) clear} |
Greater or Equal | Signed integer comparison gave greater than or equal |
| BLT | (N EOR V) =1 {(N set and V clear) or (N clear and V set)} |
Less Than | Signed integer comparison gave less than |
| BGT | (Z OR (N EOR V)) =0 {((N and V) set or clear) and Z clear} |
Greater Than | Signed integer comparison gave greater than |
| BLE | (Z OR (N EOR V)) =1 {(N set and V clear) or (N clear and V set) or Z set} |
Less or Equal | Signed integer comparison gave less than or equal |
The BCC instruction is equivalent to BLO; likewise the BCS instruction is equivalent to BHS.