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• 3. Assembly Language Operations
• The Current Program Status Register
• Comparison Operations
• Branches and Conditional Execution
  • Basic Branching
  • Conditional Branches
  • Conditional Branch Instructions
  • Conditional Execution

Conditional Execution

Unlike most processor architectures, all instructions in the ARM assembly language can be conditionally executed.

	CMP	r0, #10	; compare the value in r0 with the value 10
	BEQ	jumpaway	; if the condition code indicates an equal comparison,
			; branch to the jumpaway label
	ADD	r1, r1, r0	; add the value in r0 to r1 and store the result in r1
	SUB	r2, r2, r0	; subtract the value in r0 from r2 and store the result
			; in r2
jumpaway	...

This can be rewritten as:

CMP	r0, #10	; compare the value in r0 with the value 10
ADDNE	r1, r1, r0	; add the value in r0 to r1 and store the result in r1
SUBNE	r2, r2, r0	; subtract the value in r0 from r2 and store the result
		; in r2
...		; other code now follows

The ADDNE and SUBNE instructions are executed only if the Z bit is "0", i.e. the CMP instruction had a non-zero result and cleared the Z bit.

This form of conditional execution is efficient if the conditional sequence is only three or less instructions. For longer sequences, it is more efficient to use proper loops and conventional branching.

The "S" suffix can be appended to instructions with the conditional suffices, enabling them to adjust the condition codes. However this can lead to unexpected behaviour in succeeding instructions.

Let r0 be 4, r1 be -4, and r2 be 7. Alter the code from above to be as follows:

CMP	r0, #10	; compare the value in r0 with the value 10
ADDNE	r1, r1, r0	; r0 ≠10, so Z is 0, so r1 = -4 + 4, and Z is now set
SUBNE	r2, r2, r0	; Z is set (i.e. "1"), so SUBNE is not executed
...		; other code now follows

The conditional suffix mnemonics are the same as for conditional branches:

Suffix	Condition Test	Meaning
EQ	Z=1	Equal
NE	Z=0	Not Equal
CS	C=1	Carry Set (Unsigned Higher or Same)
CC	C=1	Carry Clear (Unsigned Lower than)
MI	N=1	Minus
PL	N=0	Plus
VS	V=1	Overflow Set
VC	V=0	Overflow Clear
HI	((NOT C) OR Z) =0 {C set and Z clear}	Higher unsigned
LS	((NOT C) OR Z) =1 {C set or Z clear}	Lower or same unsigned
GE	(N EOR V) =0 {(N and V) set or (N and V) clear}	Greater or Equal
LT	(N EOR V) =1 {(N set and V clear) or (N clear and V set)}	Less Than
GT	(Z OR (N EOR V)) =0 {((N and V) set or clear) and Z clear}	Greater Than
LE	(Z OR (N EOR V)) =1 {(N set and V clear) or (N clear and V set) or Z set}	Less or Equal