Advanced Topics

Basics

In previous lectures, two of the three classes of data transfer instructions have been explored, namely register moves (i.e. MOV and MVN) and single register load and stores (LDR and STR). In the ARM architecture, there is a third category, namely the multiple register load and store instructions. These instructions can load data from or store data to any subset of the sixteen general-purpose registers (i.e. r0 through to r15).

One register is used as a base address register storing the memory address location where values will be retrieved from or stored to.

An example of a multiple register load instruction is:

LDMIA r1, {r2, r3, r5} ; value in r1 is the base address
    ; set r2 equal to value at base address
    ; set r3 equal to value at base address +4
    ; set r5 equal to value at base address +8

Load Multiple in action

Load Multiple in action

An example of a multiple register store instruction is:

STMIA r1, {r2, r3, r5} ; value in r1 is the base address
    ; set value at base address equal to r2
    ; set value at base address+4 equal to r3
    ; set value at base address+8 equal to r5

Store Multiple in action

Store Multiple in action

Any registers can be specified in these instructions, including r15 (the Program Counter). However any change to the contents of r15 forces a branch and, in most cases, should be avoided.