Microprocessor and Memory Basics

Address Decoder

The animation below shows a "one out of 2n decoder" where n = 2. Only one output is high at any given time.

The word select lines are driven from the "one out of 2n decoder". Thus only one word select line is driven high at any time.

Word selection

Word selection

The diagram below shows how the internal signals data in, data out, and write enable are connected to the external data bus wires, the read/write wire and chip select.

Connections of internal signals to external wires

Connections of internal signals to external wires

If address decoding was performed by a single decoder, it would be a massive block of circuitry. Instead most architectures use a hierarchy of decoders to break the problem down into more manageable pieces. Usually the last stage of decoding (e.g. determining which of the 220 locations on the chip is required) is performed inside the memory chip itself.